1. Field of the Invention
The present invention relates to a register control circuit.
2. Description of the Prior Art
Generally, a variety of active devices such as, for example, CPU, CRTC, modem and etc. comprise therein registers for control of various functions, respectively. Recently, as the functions of the devices have become complex and diversified, more registers have been present for control of the functions. For the purpose of control of such a number of registers, there has been proposed a method of using a number of addresses thereby to increase an integration of the device and to reduce the number of pins of the device.
Referring to FIG. 1, there is shown a 16-CE (CHIP ENABLE) logic utilizing a 4.times.16 decoder, as a representative one of conventional methods of controlling the registers in the devices. In the method in FIG. 1, for example, at least 4 addresses are required to control 16 internal registers. Similarly, 6 addresses may be required to control 64 registers. In other words, a number of addresses are required to control the registers, resulting in a complexity of the circuit. In order to make up for such a drawback, there may be used an index register, as will be described later.
Referring to FIG. 2, there is shown a block diagram of a conventional register control circuit utilizing index registers. Each of the index registers is used as a pointer for indicating registers in a corresponding one of register blocks. In this case, addresses are required merely to designate the index registers. However, the conventional register control circuit in FIG. 2 has a disadvantage, in that a pointer value corresponding to an address of a register to be control led is written into the corresponding index register whenever the register control operation is performed.